Semiconductor integrated circuits with a plurality of semiconductor layers are fabricated by deposition, photolithography, etching, implantation, and thermal processes, repeatedly. In photolithography, relative alignment accuracy of patterns transferred on semiconductor layers is critical for semiconductor device fabrication.
FIG. 1A shows a top view of a wafer 1 which is divided into several zones by scribe lines. A plurality of checking patterns are exposed inside predetermined zones 50. The checking patterns are arranged vertically to each other to measure the relative alignment error between the patterns on adjacent semiconductor layers in two dimensions. When the checking patterns on separate semiconductor layers align accurately, the resulting target patterns 60 align with each other accurately. FIG. 1B shows checking patterns defined by conventional photomask exposing. In FIG. 1B, a rectangular checking pattern 12 is defined on a first semiconductor layer 10 and a square checking pattern 22 is defined on a second semiconductor layer 20, wherein the rectangular checking pattern 12 lies at the center of the square checking pattern 22 and the four sides of the rectangular checking pattern 12 are parallel to the four sides of the square checking pattern 22 correspondingly. When the rectangular checking pattern 12 is located at the center of the square checking pattern 22, the target patterns on the other zones of the first semiconductor layer 10 are accurately aligned with the target patterns on the other zones of the second semiconductor layer 20. Furthermore, as shown in FIG. 1B, a rectangular checking pattern 12 is defined on a first semiconductor layer 10 and a square checking pattern 32 is defined on a third semiconductor layer 30, wherein the rectangular checking pattern 12 lies at the center of the square checking pattern 32 and the four sides of the rectangular checking pattern 12 are parallel to the four sides of the square checking pattern 32 correspondingly. When the rectangular checking pattern 12 is located at the center of the square checking pattern 32, target patterns on the other zones of the first semiconductor layer 10 are accurately aligned with target patterns on the other zones of the third semiconductor layer 30.
Moreover, as shown in FIG. 1B, two rectangular checking patterns 42A and 42B are formed in a fourth semiconductor layer 40, wherein the rectangular checking pattern 42A is parallel to the rectangular checking pattern 12 in the Y-axis and the rectangular checking pattern 42B is parallel to the rectangular checking pattern 22 in the X-axis.
The disadvantage of conventional alignment of checking patterns is that target patterns on the third and fourth semiconductor layers 30 and 40 frequently misalign in the X-axis. Generally, the square checking pattern 32 on the third semiconductor layer 30 is assumed to be aligned with the square checking pattern 22 on the second semiconductor layer 20 along the X-axis, and therefore, when the rectangular checking pattern 42b on the fourth semiconductor layer 40 is aligned with the square checking pattern 22 on the second semiconductor layer 20 in the X-axis, the target patterns on the fourth semiconductor layer 40 should be aligned with the target patterns on the third semiconductor layer 30 along the X-axis. However, the square checking pattern 32 on the third semiconductor layer 30 may not align precisely with the square checking pattern 22 on the second semiconductor layer 20 along the X-axis, and the resulting target patterns on the fourth semiconductor layer 40 misalign with the target patterns on the third semiconductor layer 30 along the X-axis.